复杂模块接口的独立设计

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The MAX14885E, a fully integrated low-capacitance VGA dual-graphics crossover switch, connects a VGA source to a VGA monitor. This applicaTIon note explains the proper sequencing of the MAX14885Es two

The MAX14885E, a fully integrated low-capacitance VGA dual-graphics crossover switch, connects a VGA source to a VGA monitor. This applicaTIon note explains the proper sequencing of the MAX14885E’s two power supplies, VCC and VL, on power-up.

IntroducTIon

TheMAX14885E, a 2:2VGAswitch, connects a VGAsourceto a VGA monitor. To ease direct connecTIon to graphics controllers or theASIC, the MAX14885E has two supplies:VCC, a 5V ±5% supply, drives the VGA side interface; and the VLsupply sets the logic switching thresholds on the digital input pins (EN, S00, S01, S10, S11,SHA, SHB, SVA, and SVB). This applicaTIon note documents the proper sequencing of the VCCand VLpower supplies on power-up.

Proper Power Sequencing

To ensure that the MAX14885E operates correctly, the VCCand VLsupplies must be properly sequenced. It is easiest to understand the correct sequencing conditions if we split the discussion into two cases: first, when VLrises before (or coincidently) with VCC; and second, the case when VLrises after VCC.

Case 1: When VLRises Before VCC

The MAX14885E powers up properly when VLrises before VCCrises or when it rises coincidently with VCC. This is shown inFigures 1and2.
Figure 1. VLrises in advance of the VCCrising, resulting in a good power-up.
Figure 2. VLrises coincidently with the VCCrising, resulting in a good power-up.

Case 2: When VLRises After VCC

In the situation where VLstarts rising after VCCbegins to rise at power-up, some care must be taken(Figure 3). For proper power-up, users must ensure that VCChas settled before VLstarts rising.
Figure 3. VLrises too soon after VCC, resulting in a bad power-up.VLneeds to start rising after VCChas settled (outside of the red triangle illustrated inFigure 4).
Figure 4. VLrises after VCChas settled, resulting in a good power-up.To provide a safety margin against variations in production and sequencing external power-supply circuits, it is recommended that the delay from VCCrising to VLrising be at least twice the rise time of the VCCsupply.
Figure 5. Definition and requirements for safe timing with margin.Detailed Analysis of Power SequencingOften, power supply rails rise as shown in the previous figures. In some cases, however, the point where a power-supply transition ends is not so clear. This section describes a quantitative means to analyze a given specific scenario where VLrises after VCC. This method ensures that there is sufficient delay for correct power-up sequencing.

To determine this, four time measurements must be taken. Two of these measurements are with respect to specificvoltagelevels on VCC, and the other two are with respect to specific voltage levels on VL. All four measurements are to be taken from a single scope capture.

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